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471 lines
17 KiB
C++
471 lines
17 KiB
C++
/* Copyright (c) 2006, Google Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following disclaimer
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* in the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Google Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* ---
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* Author: Sanjay Ghemawat
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*/
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// Implementation of atomic operations for x86. This file should not
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// be included directly. Clients should instead include
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// "base/atomicops.h".
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#ifndef BASE_ATOMICOPS_INTERNALS_X86_H_
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#define BASE_ATOMICOPS_INTERNALS_X86_H_
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typedef int32_t Atomic32;
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#define BASE_HAS_ATOMIC64 1 // Use only in tests and base/atomic*
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// NOTE(vchen): x86 does not need to define AtomicWordCastType, because it
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// already matches Atomic32 or Atomic64, depending on the platform.
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// This struct is not part of the public API of this module; clients may not
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// use it.
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// Features of this x86. Values may not be correct before main() is run,
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// but are set conservatively.
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struct AtomicOps_x86CPUFeatureStruct {
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bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
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// after acquire compare-and-swap.
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bool has_sse2; // Processor has SSE2.
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bool has_cmpxchg16b; // Processor supports cmpxchg16b instruction.
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};
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extern struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures;
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#define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
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namespace base {
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namespace subtle {
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typedef int64_t Atomic64;
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// 32-bit low-level operations on any platform.
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inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 prev;
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__asm__ __volatile__("lock; cmpxchgl %1,%2"
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: "=a" (prev)
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: "q" (new_value), "m" (*ptr), "0" (old_value)
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: "memory");
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return prev;
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}
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inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
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Atomic32 new_value) {
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__asm__ __volatile__("xchgl %1,%0" // The lock prefix is implicit for xchg.
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: "=r" (new_value)
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: "m" (*ptr), "0" (new_value)
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: "memory");
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return new_value; // Now it's the previous value.
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}
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inline Atomic32 Acquire_AtomicExchange(volatile Atomic32* ptr,
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Atomic32 new_value) {
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Atomic32 old_val = NoBarrier_AtomicExchange(ptr, new_value);
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if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
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__asm__ __volatile__("lfence" : : : "memory");
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}
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return old_val;
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}
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inline Atomic32 Release_AtomicExchange(volatile Atomic32* ptr,
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Atomic32 new_value) {
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// xchgl already has release memory barrier semantics.
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return NoBarrier_AtomicExchange(ptr, new_value);
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}
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inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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Atomic32 temp = increment;
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__asm__ __volatile__("lock; xaddl %0,%1"
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: "+r" (temp), "+m" (*ptr)
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: : "memory");
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// temp now holds the old value of *ptr
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return temp + increment;
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}
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inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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Atomic32 temp = increment;
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__asm__ __volatile__("lock; xaddl %0,%1"
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: "+r" (temp), "+m" (*ptr)
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: : "memory");
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// temp now holds the old value of *ptr
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if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
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__asm__ __volatile__("lfence" : : : "memory");
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}
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return temp + increment;
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}
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inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
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__asm__ __volatile__("lfence" : : : "memory");
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}
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return x;
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}
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inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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}
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inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
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*ptr = value;
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}
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#if defined(__x86_64__)
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// 64-bit implementations of memory barrier can be simpler, because it
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// "mfence" is guaranteed to exist.
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inline void GMemoryBarrier() {
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__asm__ __volatile__("mfence" : : : "memory");
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}
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inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
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*ptr = value;
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GMemoryBarrier();
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}
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#else
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inline void MemoryBarrier() {
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if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
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__asm__ __volatile__("mfence" : : : "memory");
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} else { // mfence is faster but not present on PIII
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Atomic32 x = 0;
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Acquire_AtomicExchange(&x, 0);
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}
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}
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inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
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if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
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*ptr = value;
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__asm__ __volatile__("mfence" : : : "memory");
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} else {
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Acquire_AtomicExchange(ptr, value);
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}
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}
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#endif
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inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
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ATOMICOPS_COMPILER_BARRIER();
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*ptr = value; // An x86 store acts as a release barrier.
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// See comments in Atomic64 version of Release_Store(), below.
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}
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inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
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return *ptr;
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}
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inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
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Atomic32 value = *ptr; // An x86 load acts as a acquire barrier.
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// See comments in Atomic64 version of Release_Store(), below.
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ATOMICOPS_COMPILER_BARRIER();
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return value;
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}
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inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
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GMemoryBarrier();
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return *ptr;
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}
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#if defined(__x86_64__)
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// 64-bit low-level operations on 64-bit platform.
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inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 prev;
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__asm__ __volatile__("lock; cmpxchgq %1,%2"
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: "=a" (prev)
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: "q" (new_value), "m" (*ptr), "0" (old_value)
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: "memory");
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return prev;
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}
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inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
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Atomic64 new_value) {
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__asm__ __volatile__("xchgq %1,%0" // The lock prefix is implicit for xchg.
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: "=r" (new_value)
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: "m" (*ptr), "0" (new_value)
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: "memory");
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return new_value; // Now it's the previous value.
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}
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inline Atomic64 Acquire_AtomicExchange(volatile Atomic64* ptr,
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Atomic64 new_value) {
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Atomic64 old_val = NoBarrier_AtomicExchange(ptr, new_value);
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if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
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__asm__ __volatile__("lfence" : : : "memory");
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}
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return old_val;
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}
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inline Atomic64 Release_AtomicExchange(volatile Atomic64* ptr,
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Atomic64 new_value) {
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// xchgq already has release memory barrier semantics.
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return NoBarrier_AtomicExchange(ptr, new_value);
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}
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inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 increment) {
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Atomic64 temp = increment;
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__asm__ __volatile__("lock; xaddq %0,%1"
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: "+r" (temp), "+m" (*ptr)
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: : "memory");
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// temp now contains the previous value of *ptr
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return temp + increment;
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}
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inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 increment) {
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Atomic64 temp = increment;
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__asm__ __volatile__("lock; xaddq %0,%1"
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: "+r" (temp), "+m" (*ptr)
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: : "memory");
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// temp now contains the previous value of *ptr
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if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
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__asm__ __volatile__("lfence" : : : "memory");
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}
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return temp + increment;
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}
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inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
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*ptr = value;
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}
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inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
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*ptr = value;
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GMemoryBarrier();
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}
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inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
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ATOMICOPS_COMPILER_BARRIER();
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*ptr = value; // An x86 store acts as a release barrier
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// for current AMD/Intel chips as of Jan 2008.
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// See also Acquire_Load(), below.
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// When new chips come out, check:
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// IA-32 Intel Architecture Software Developer's Manual, Volume 3:
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// System Programming Guide, Chatper 7: Multiple-processor management,
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// Section 7.2, Memory Ordering.
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// Last seen at:
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// http://developer.intel.com/design/pentium4/manuals/index_new.htm
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//
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// x86 stores/loads fail to act as barriers for a few instructions (clflush
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// maskmovdqu maskmovq movntdq movnti movntpd movntps movntq) but these are
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// not generated by the compiler, and are rare. Users of these instructions
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// need to know about cache behaviour in any case since all of these involve
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// either flushing cache lines or non-temporal cache hints.
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}
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inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
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return *ptr;
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}
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inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
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Atomic64 value = *ptr; // An x86 load acts as a acquire barrier,
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// for current AMD/Intel chips as of Jan 2008.
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// See also Release_Store(), above.
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ATOMICOPS_COMPILER_BARRIER();
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return value;
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}
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inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
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GMemoryBarrier();
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return *ptr;
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}
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#else // defined(__x86_64__)
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// 64-bit low-level operations on 32-bit platform.
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#if !((__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 1))
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// For compilers older than gcc 4.1, we use inline asm.
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//
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// Potential pitfalls:
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//
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// 1. %ebx points to Global offset table (GOT) with -fPIC.
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// We need to preserve this register.
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// 2. When explicit registers are used in inline asm, the
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// compiler may not be aware of it and might try to reuse
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// the same register for another argument which has constraints
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// that allow it ("r" for example).
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inline Atomic64 __sync_val_compare_and_swap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 prev;
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__asm__ __volatile__("push %%ebx\n\t"
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"movl (%3), %%ebx\n\t" // Move 64-bit new_value into
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"movl 4(%3), %%ecx\n\t" // ecx:ebx
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"lock; cmpxchg8b (%1)\n\t"// If edx:eax (old_value) same
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"pop %%ebx\n\t"
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: "=A" (prev) // as contents of ptr:
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: "D" (ptr), // ecx:ebx => ptr
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"0" (old_value), // else:
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"S" (&new_value) // old *ptr => edx:eax
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: "memory", "%ecx");
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return prev;
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}
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#endif // Compiler < gcc-4.1
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inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_val,
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Atomic64 new_val) {
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return __sync_val_compare_and_swap(ptr, old_val, new_val);
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}
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inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
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Atomic64 new_val) {
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Atomic64 old_val;
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do {
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old_val = *ptr;
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} while (__sync_val_compare_and_swap(ptr, old_val, new_val) != old_val);
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return old_val;
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}
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inline Atomic64 Acquire_AtomicExchange(volatile Atomic64* ptr,
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Atomic64 new_val) {
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Atomic64 old_val = NoBarrier_AtomicExchange(ptr, new_val);
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if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
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__asm__ __volatile__("lfence" : : : "memory");
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}
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return old_val;
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}
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inline Atomic64 Release_AtomicExchange(volatile Atomic64* ptr,
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Atomic64 new_val) {
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return NoBarrier_AtomicExchange(ptr, new_val);
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}
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inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 increment) {
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Atomic64 old_val, new_val;
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do {
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old_val = *ptr;
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new_val = old_val + increment;
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} while (__sync_val_compare_and_swap(ptr, old_val, new_val) != old_val);
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return old_val + increment;
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}
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inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 increment) {
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Atomic64 new_val = NoBarrier_AtomicIncrement(ptr, increment);
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if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
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__asm__ __volatile__("lfence" : : : "memory");
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}
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return new_val;
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}
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inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
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__asm__ __volatile__("movq %1, %%mm0\n\t" // Use mmx reg for 64-bit atomic
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"movq %%mm0, %0\n\t" // moves (ptr could be read-only)
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"emms\n\t" // Empty mmx state/Reset FP regs
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: "=m" (*ptr)
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: "m" (value)
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: // mark the FP stack and mmx registers as clobbered
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"st", "st(1)", "st(2)", "st(3)", "st(4)",
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"st(5)", "st(6)", "st(7)", "mm0", "mm1",
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"mm2", "mm3", "mm4", "mm5", "mm6", "mm7");
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}
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inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
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NoBarrier_Store(ptr, value);
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MemoryBarrier();
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}
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inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
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ATOMICOPS_COMPILER_BARRIER();
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NoBarrier_Store(ptr, value);
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}
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inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
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Atomic64 value;
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__asm__ __volatile__("movq %1, %%mm0\n\t" // Use mmx reg for 64-bit atomic
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"movq %%mm0, %0\n\t" // moves (ptr could be read-only)
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"emms\n\t" // Empty mmx state/Reset FP regs
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: "=m" (value)
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: "m" (*ptr)
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: // mark the FP stack and mmx registers as clobbered
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"st", "st(1)", "st(2)", "st(3)", "st(4)",
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"st(5)", "st(6)", "st(7)", "mm0", "mm1",
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"mm2", "mm3", "mm4", "mm5", "mm6", "mm7");
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return value;
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}
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inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
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Atomic64 value = NoBarrier_Load(ptr);
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ATOMICOPS_COMPILER_BARRIER();
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return value;
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}
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inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
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MemoryBarrier();
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return NoBarrier_Load(ptr);
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}
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#endif // defined(__x86_64__)
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inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
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__asm__ __volatile__("lfence" : : : "memory");
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}
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return x;
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}
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inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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}
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} // namespace base::subtle
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} // namespace base
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#undef ATOMICOPS_COMPILER_BARRIER
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#endif // BASE_ATOMICOPS_INTERNALS_X86_H_
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