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https://github.com/beefytech/Beef.git
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Trailing whitespace trimming
This commit is contained in:
Brian Fiete
parent
06425735d9
commit
7f328385db
88 changed files with 9577 additions and 9850 deletions
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@ -159,10 +159,10 @@ bool X86Instr::StackAdjust(uint32& adjust)
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if (mMCInst.getOpcode() != X86::SUB32ri8)
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return true;
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auto operand0 = mMCInst.getOperand(0);
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if (operand0.getReg() != llvm::X86::ESP)
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return true;
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return true;
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auto operand2 = mMCInst.getOperand(2);
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if (!operand2.isImm())
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return false;
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@ -191,7 +191,7 @@ bool X86Instr::IsReturn()
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}
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bool X86Instr::IsRep(bool& isPrefixOnly)
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{
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{
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auto instFlags = mMCInst.getFlags();
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if ((instFlags & (X86::IP_HAS_REPEAT_NE | X86::IP_HAS_REPEAT)) != 0)
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{
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@ -208,7 +208,7 @@ bool X86Instr::IsRep(bool& isPrefixOnly)
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}
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bool X86Instr::IsLoadAddress()
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{
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{
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const MCInstrDesc &instDesc = mX86->mInstrInfo->get(mMCInst.getOpcode());
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if (instDesc.NumOperands >= 6)
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{
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@ -234,25 +234,25 @@ static int ConvertRegNum(const MCOperand& operand)
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case llvm::X86::CL:
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case llvm::X86::CH:
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case llvm::X86::ECX:
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return X86Reg_ECX;
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return X86Reg_ECX;
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case llvm::X86::DL:
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case llvm::X86::DH:
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case llvm::X86::EDX:
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return X86Reg_EDX;
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return X86Reg_EDX;
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case llvm::X86::BL:
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case llvm::X86::BH:
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case llvm::X86::EBX:
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return X86Reg_EBX;
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return X86Reg_EBX;
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case llvm::X86::ESP:
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return X86Reg_ESP;
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return X86Reg_ESP;
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case llvm::X86::EBP:
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return X86Reg_EBP;
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return X86Reg_EBP;
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case llvm::X86::ESI:
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return X86Reg_ESI;
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return X86Reg_ESI;
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case llvm::X86::EDI:
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return X86Reg_EDI;
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return X86Reg_EDI;
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case llvm::X86::EIP:
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return X86Reg_EIP;
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return X86Reg_EIP;
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case llvm::X86::EFLAGS:
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return X86Reg_EFL;
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@ -272,7 +272,7 @@ static int ConvertRegNum(const MCOperand& operand)
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return X86Reg_FPST6;
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case llvm::X86::ST7:
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return X86Reg_FPST7;
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case llvm::X86::XMM0:
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return X86Reg_M128_XMM0;
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case llvm::X86::XMM1:
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@ -299,9 +299,9 @@ bool X86Instr::GetIndexRegisterAndOffset(int* outRegister, int* outOffset)
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const MCInstrDesc &instDesc = mX86->mInstrInfo->get(mMCInst.getOpcode());
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auto form = (instDesc.TSFlags & llvm::X86II::FormMask);
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if ((form == llvm::X86II::MRMDestMem) || (form == llvm::X86II::MRMSrcMem) ||
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if ((form == llvm::X86II::MRMDestMem) || (form == llvm::X86II::MRMSrcMem) ||
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((form >= llvm::X86II::MRM0m) && (form <= llvm::X86II::MRM7m)))
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{
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{
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auto baseReg = mMCInst.getOperand(llvm::X86::AddrBaseReg);
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auto scaleAmt = mMCInst.getOperand(llvm::X86::AddrScaleAmt);
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auto indexReg = mMCInst.getOperand(llvm::X86::AddrIndexReg);
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@ -320,12 +320,12 @@ bool X86Instr::GetIndexRegisterAndOffset(int* outRegister, int* outOffset)
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if ((baseReg.isReg()) &&
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(scaleAmt.isImm()) && (scaleAmt.getImm() == 1) &&
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(indexReg.isReg()) && (indexReg.getReg() == llvm::X86::NoRegister) &&
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(addrDisp.isImm()))
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(addrDisp.isImm()))
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{
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int regNum = ConvertRegNum(baseReg);
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if (regNum == -1)
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return false;
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*outRegister = regNum;
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*outRegister = regNum;
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*outOffset = (int)addrDisp.getImm();
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return true;
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}
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@ -336,11 +336,11 @@ bool X86Instr::GetIndexRegisterAndOffset(int* outRegister, int* outOffset)
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bool X86Instr::GetImmediate(uint32* outImm)
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{
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const MCInstrDesc &instDesc = mX86->mInstrInfo->get(mMCInst.getOpcode());
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auto immediateType = (instDesc.TSFlags & llvm::X86II::ImmMask);
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if ((immediateType == 0) && (mMCInst.getNumOperands() < 6))
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return false;
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auto immOp = mMCInst.getOperand(5);
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if (!immOp.isImm())
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return false;
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@ -376,9 +376,9 @@ void X86Instr::MarkRegsUsed(Array<RegForm>& regsUsed, bool overrideForm)
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}
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uint32 X86Instr::GetTarget(Debugger* debugger, X86CPURegisters* registers)
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{
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{
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const MCInstrDesc &instDesc = mX86->mInstrInfo->get(mMCInst.getOpcode());
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if (mMCInst.getNumOperands() < 1)
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return 0;
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@ -389,7 +389,7 @@ uint32 X86Instr::GetTarget(Debugger* debugger, X86CPURegisters* registers)
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opIdx = 4;
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operand = mMCInst.getOperand(opIdx);
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}
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if (operand.isImm())
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{
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auto targetAddr = (uint32)operand.getImm();
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@ -418,7 +418,7 @@ X86CPU::X86CPU() :
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mInstrInfo = NULL;
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mInstPrinter = NULL;
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//InitializeAllTargets();
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//InitializeAllTargets();
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auto& TheX86_32Target = getTheX86_32Target();
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@ -438,7 +438,7 @@ X86CPU::X86CPU() :
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//TargetOptions targetOptions;
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//TargetMachine* targetMachine = TheX86_32Target.createTargetMachine(triple, "x86", "", targetOptions);
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//const MCInstrInfo* MII = targetMachine->getSubtargetImpl()->getInstrInfo();
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//const MCInstrInfo* MII = targetMachine->getSubtargetImpl()->getInstrInfo();
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//STI->getIntr
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mInstrInfo = TheX86_32Target.createMCInstrInfo();
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@ -452,11 +452,11 @@ X86CPU::X86CPU() :
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mMCContext->setObjectFileInfo(mMCObjectFileInfo);
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MCDisassembler *disAsm = TheX86_32Target.createMCDisassembler(*mSubtargetInfo, *mMCContext);
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mDisAsm = disAsm;
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mDisAsm = disAsm;
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//TODO: LLVM3.8 - changed params
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/*mInstPrinter = TheX86_32Target.createMCInstPrinter(1, *mAsmInfo,
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*mInstrInfo, *mRegisterInfo, *mSubtargetInfo);*/
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*mInstrInfo, *mRegisterInfo, *mSubtargetInfo);*/
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mInstPrinter = TheX86_32Target.createMCInstPrinter(Triple(triple), 1, *mAsmInfo,
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*mInstrInfo, *mRegisterInfo);
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@ -471,7 +471,7 @@ X86CPU::X86CPU() :
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extern "C" void LLVMShutdown();
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X86CPU::~X86CPU()
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{
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{
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delete mInstPrinter;
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delete mDisAsm;
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delete mMCContext;
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@ -485,11 +485,11 @@ X86CPU::~X86CPU()
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}
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bool X86CPU::Decode(uint32 address, DbgModuleMemoryCache* memoryCache, X86Instr* inst)
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{
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{
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inst->mAddress = address;
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inst->mX86 = this;
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uint64 size = 0;
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uint64 size = 0;
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uint8 data[15];
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memoryCache->Read(address, data, 15);
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@ -504,15 +504,15 @@ bool X86CPU::Decode(uint32 address, DbgModuleMemoryCache* memoryCache, X86Instr*
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bool X86CPU::Decode(uint32 baseAddress, const uint8* dataBase, int dataLength, const uint8* dataPtr, X86Instr* inst)
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{
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//X86GenericDisassembler assembler;
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//DisasmMemoryObject region((uint8*)dataBase, dataLength, baseAddress);
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//std::memorystream
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uint32 address = baseAddress + (uint32)(dataPtr - dataBase);
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inst->mAddress = address;
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inst->mX86 = this;
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uint64 size = 0;
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uint64 size = 0;
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//TODO: LLVM3.8
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//MCDisassembler::DecodeStatus S = mDisAsm->getInstruction(inst->mMCInst, size, region, address, nulls(), inst->mAnnotationStream);
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@ -526,7 +526,7 @@ bool X86CPU::Decode(uint32 baseAddress, const uint8* dataBase, int dataLength, c
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void X86CPU::GetNextPC(uint32 baseAddress, const uint8* dataBase, int dataLength, const uint8* dataPtr, uint32* regs, uint32 nextPCs[2])
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{
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//DisasmMemoryObject region((uint8*) dataBase, dataLength, baseAddress);
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//DisasmMemoryObject region((uint8*) dataBase, dataLength, baseAddress);
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uint32 address = baseAddress + (uint32)(dataPtr - dataBase);
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uint64 size = 0;
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@ -535,17 +535,16 @@ void X86CPU::GetNextPC(uint32 baseAddress, const uint8* dataBase, int dataLength
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mDisAsm->CommentStream = &nulls();
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ArrayRef<uint8_t> dataArrayRef(dataPtr, dataLength - (dataPtr - dataBase));
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MCDisassembler::DecodeStatus S = mDisAsm->getInstruction(mcInst, size, dataArrayRef, address, nulls());
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}
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bool X86CPU::IsReturnInstruction(X86Instr* inst)
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{
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const MCInstrDesc &instDesc = mInstrInfo->get(inst->mMCInst.getOpcode());
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return (instDesc.getFlags() & (1<<MCID::Return)) != 0;
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return (instDesc.getFlags() & (1<<MCID::Return)) != 0;
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}
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String X86CPU::InstructionToString(X86Instr* inst, uint32 addr)
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{
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{
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StringRef annotationsStr;
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SmallVector<char, 256> insnStr;
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@ -553,8 +552,8 @@ String X86CPU::InstructionToString(X86Instr* inst, uint32 addr)
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//mInstPrinter->CurPCRelImmOffset = addr + inst->GetLength();
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mInstPrinter->printInst(&inst->mMCInst, addr, annotationsStr, *mSubtargetInfo, OS);
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//OS.flush();
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//llvm::StringRef str = OS.str();
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//llvm::StringRef str = OS.str();
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String result;
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for (int idx = 0; idx < (int)insnStr.size(); idx++)
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{
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@ -570,8 +569,8 @@ String X86CPU::InstructionToString(X86Instr* inst, uint32 addr)
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else
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result.Append(c);
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}
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/*String result = String(insnStr.data(), insnStr.size());
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/*String result = String(insnStr.data(), insnStr.size());
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for (int i = 0; i < (int)result.length(); i++)
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{
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if (result[i] == '\t')
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@ -671,12 +670,12 @@ int X86CPU::GetOpcodesForMnemonic(const StringImpl& mnemonic, Array<int>& outOpc
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String s(mnemonic);
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std::transform(s.begin(), s.end(), s.begin(), ::tolower);
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std::pair<StringToOpcodeMap::iterator, StringToOpcodeMap::iterator> range = mStringToOpcodeMap.equal_range(s);
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outOpcodes.Clear();
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for (StringToOpcodeMap::iterator it = range.first; it != range.second; ++it)
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outOpcodes.push_back(it->second);
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return (int)outOpcodes.size();
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return (int)outOpcodes.size();
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}
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void X86CPU::GetClobbersForMnemonic(const StringImpl& mnemonic, int argCount, Array<int>& outImplicitClobberRegNums, int& outClobberArgCount, bool& outMayClobberMem)
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