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https://github.com/beefytech/Beef.git
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Trailing whitespace trimming
This commit is contained in:
Brian Fiete
parent
06425735d9
commit
7f328385db
88 changed files with 9577 additions and 9850 deletions
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@ -54,7 +54,7 @@ const char* X64CPURegisters::sCPURegisterNames[] =
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"NONE",
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// integer general registers (DO NOT REORDER THESE; must exactly match DbgModule x86 register mappings)
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"RAX",
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"RAX",
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"RDX",
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"RCX",
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"RBX",
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@ -69,7 +69,7 @@ const char* X64CPURegisters::sCPURegisterNames[] =
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"R12",
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"R13",
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"R14",
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"R15",
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"R15",
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"RIP",
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"EFL",
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"GS",
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@ -88,7 +88,7 @@ const char* X64CPURegisters::sCPURegisterNames[] =
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"R13D",
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"R14D",
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"R15D",
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"AX",
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"DX",
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"CX",
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@ -141,7 +141,7 @@ const char* X64CPURegisters::sCPURegisterNames[] =
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"MM4",
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"MM5",
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"MM6",
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"MM7",
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"MM7",
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"XMM0_f64",
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"XMM1_f64",
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@ -354,7 +354,7 @@ bool X64Instr::IsRep(bool& isPrefixOnly)
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bool X64Instr::IsReturn()
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{
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const MCInstrDesc &instDesc = mX64->mInstrInfo->get(mMCInst.getOpcode());
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const MCInstrDesc &instDesc = mX64->mInstrInfo->get(mMCInst.getOpcode());
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return (instDesc.getFlags() & (1 << MCID::Return)) != 0;
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}
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@ -402,7 +402,7 @@ static int ConvertRegNum(const MCOperand& operand)
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return X64Reg_RBP;
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case llvm::X86::RSP:
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return X64Reg_RSP;
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case llvm::X86::R8:
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case llvm::X86::R8D:
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case llvm::X86::R8W:
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@ -507,7 +507,7 @@ static int ConvertRegNum(const MCOperand& operand)
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case llvm::X86::XMM14:
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return X64Reg_M128_XMM14;
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case llvm::X86::XMM15:
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return X64Reg_M128_XMM15;
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return X64Reg_M128_XMM15;
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}
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return -1;
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@ -573,13 +573,13 @@ bool X64Instr::GetImmediate(uint64* outImm)
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int X64Instr::GetJmpState(int flags)
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{
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const MCInstrDesc &instDesc = mX64->mInstrInfo->get(mMCInst.getOpcode());
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const MCInstrDesc &instDesc = mX64->mInstrInfo->get(mMCInst.getOpcode());
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if ((instDesc.getFlags() & (1 << MCID::Branch)) == 0)
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return -1;
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if (mMCInst.getNumOperands() < 1)
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return 0;
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#define FLAGVAR(abbr, name) int flag##abbr = ((flags & ((uint64)1 << X64CPURegisters::GetFlagBitForRegister(X64Reg_FLAG_##abbr##_##name))) != 0) ? 1 : 0
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FLAGVAR(CF, CARRY);
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FLAGVAR(PF, PARITY);
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@ -641,10 +641,10 @@ void X64Instr::MarkRegsUsed(Array<RegForm>& regsUsed, bool overrideForm)
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int opCode = instDesc.getOpcode();
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auto form = (instDesc.TSFlags & llvm::X86II::FormMask);
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/*if (opCode == 1724)
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/*if (opCode == 1724)
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{
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// MOVAPSrr is emitted for all moves between XMM registers, regardless of
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// MOVAPSrr is emitted for all moves between XMM registers, regardless of
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// their actual format, so we just copy the actual RegForm form here
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if (instDesc.getNumOperands() != 2)
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return;
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@ -655,7 +655,7 @@ void X64Instr::MarkRegsUsed(Array<RegForm>& regsUsed, bool overrideForm)
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int regNumFrom = ConvertRegNum(operand);
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if (regNumFrom == -1) // ??
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return;
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return;
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while (std::max(regNumFrom, regNumTo) >= (int)regsUsed.size())
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regsUsed.push_back(RegForm_Invalid);
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@ -680,7 +680,7 @@ void X64Instr::MarkRegsUsed(Array<RegForm>& regsUsed, bool overrideForm)
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int checkIdx = opCode * 3;
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//const MCInstrDesc &instDesc = mX64->mInstrInfo->get(mMCInst.getOpcode());
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//auto form = (instDesc.TSFlags & llvm::X86II::FormMask);
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//auto form = (instDesc.TSFlags & llvm::X86II::FormMask);
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for (int opIdx = 0; opIdx < std::min((int)instDesc.getNumOperands(), 3); opIdx++)
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{
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@ -696,7 +696,7 @@ void X64Instr::MarkRegsUsed(Array<RegForm>& regsUsed, bool overrideForm)
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regsUsed[regNum] = regForm;
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checkIdx++;
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}
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}
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}
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}
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@ -733,7 +733,7 @@ uint64 X64Instr::GetTarget(Debugger* debugger, X64CPURegisters* registers)
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if (operand.isImm())
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{
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auto targetAddr = (uint64)operand.getImm();
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auto targetAddr = (uint64)operand.getImm();
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if (instDesc.OpInfo[opIdx].OperandType == MCOI::OPERAND_PCREL)
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targetAddr += mAddress + mSize;
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return targetAddr;
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@ -756,10 +756,10 @@ bool X64Instr::PartialSimulate(Debugger* debugger, X64CPURegisters* registers)
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// auto form = (instDesc.TSFlags & llvm::X86II::FormMask);
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//
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// if ((form == llvm::X86II::MRMSrcMem) && (instDesc.NumOperands == 6))
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// {
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// {
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// auto destReg = mMCInst.getOperand(llvm::X86::AddrBaseReg);
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// if (destReg.isReg())
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// {
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// {
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// int regNum = 0;
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// int offset = 0;
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// if (GetIndexRegisterAndOffset(®Num, &offset))
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@ -767,7 +767,7 @@ bool X64Instr::PartialSimulate(Debugger* debugger, X64CPURegisters* registers)
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// uint64 addr = registers->mIntRegsArray[regNum] + offset;
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// uint64 val = 0;
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// debugger->ReadMemory(addr, 8, &val);
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//
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//
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// switch (destReg.getReg())
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// {
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//
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@ -779,7 +779,7 @@ bool X64Instr::PartialSimulate(Debugger* debugger, X64CPURegisters* registers)
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//// if ((form == llvm::X86II::MRMDestMem) || (form == llvm::X86II::MRMSrcMem) ||
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//// ((form >= llvm::X86II::MRM0m) && (form <= llvm::X86II::MRM7m)))
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//// {
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//// }
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//// }
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// }
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//
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// if (instDesc.getOpcode() == X86::XOR8rr)
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@ -792,7 +792,7 @@ bool X64Instr::PartialSimulate(Debugger* debugger, X64CPURegisters* registers)
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// if ((destReg.isReg()) && (srcReg.isReg()))
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// {
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// if (destReg.getReg() == srcReg.getReg())
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// {
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// {
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// switch (destReg.getReg())
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// {
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// case X86::AL:
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@ -817,8 +817,8 @@ X64CPU::X64CPU() :
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mInstrInfo = NULL;
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mInstPrinter = NULL;
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//InitializeAllTargets();
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//InitializeAllTargets();
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auto& TheX86_64Target = llvm::getTheX86_64Target();
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const char* triple = "x86_64-pc-mingw32";
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@ -835,7 +835,7 @@ X64CPU::X64CPU() :
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return;
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mInstrInfo = TheX86_64Target.createMCInstrInfo();
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mMCContext = new MCContext(Triple(triple), mAsmInfo, mRegisterInfo, mSubtargetInfo);
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mMCObjectFileInfo = TheX86_64Target.createMCObjectFileInfo(*mMCContext, false);
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@ -875,11 +875,11 @@ X64CPU::~X64CPU()
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}
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bool X64CPU::Decode(uint64 address, DbgModuleMemoryCache* memoryCache, X64Instr* inst)
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{
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{
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inst->mAddress = address;
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inst->mX64 = this;
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uint64 size = 0;
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uint64 size = 0;
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uint8 data[15];
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memoryCache->Read(address, data, 15);
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@ -939,7 +939,6 @@ void X64CPU::GetNextPC(uint64 baseAddress, const uint8* dataBase, int dataLength
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mDisAsm->CommentStream = &nulls();
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ArrayRef<uint8_t> dataArrayRef(dataPtr, dataLength - (dataPtr - dataBase));
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MCDisassembler::DecodeStatus S = mDisAsm->getInstruction(mcInst, size, dataArrayRef, address, nulls());
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}
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bool X64CPU::IsReturnInstruction(X64Instr* inst)
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@ -957,7 +956,7 @@ String X64CPU::InstructionToString(X64Instr* inst, uint64 addr)
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//mInstPrinter->CurPCRelImmOffset = addr + inst->GetLength();
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mInstPrinter->printInst(&inst->mMCInst, addr, annotationsStr, *mSubtargetInfo, OS);
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//OS.flush();
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//llvm::StringRef str = OS.str();
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//llvm::StringRef str = OS.str();
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String result;
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for (int idx = 0; idx < (int)insnStr.size(); idx++)
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@ -991,21 +990,21 @@ String X64CPU::InstructionToString(X64Instr* inst, uint64 addr)
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}
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DbgBreakKind X64CPU::GetDbgBreakKind(uint64 address, DbgModuleMemoryCache* memoryCache, int64* regs, int64* outObjectPtr)
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{
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{
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// We've looking for a CMP BYTE PTR [<reg>], -0x80
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// if <reg> is R12 then encoding takes an extra 2 bytes
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X64Instr inst;
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X64Instr inst;
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for (int checkLen = 5; checkLen >= 3; checkLen--)
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{
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{
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int offset = -3 - checkLen;
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if (!Decode(address + offset, memoryCache, &inst))
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continue;
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continue;
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if (inst.GetLength() != checkLen)
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continue;
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const MCInstrDesc &instDesc = mInstrInfo->get(inst.mMCInst.getOpcode());
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const MCInstrDesc &instDesc = mInstrInfo->get(inst.mMCInst.getOpcode());
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if (!instDesc.isCompare())
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continue;
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@ -1052,18 +1051,18 @@ DbgBreakKind X64CPU::GetDbgBreakKind(uint64 address, DbgModuleMemoryCache* memor
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for (int offset = 3; offset <= 3; offset++)
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{
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if (!Decode(address - offset, memoryCache, &inst))
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continue;
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continue;
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if (inst.GetLength() != 2)
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continue;
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const MCInstrDesc &instDesc = mInstrInfo->get(inst.mMCInst.getOpcode());
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const MCInstrDesc &instDesc = mInstrInfo->get(inst.mMCInst.getOpcode());
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if (!instDesc.isBranch())
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continue;
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auto immediateType = (instDesc.TSFlags & llvm::X86II::ImmMask);
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if ((immediateType == llvm::X86II::Imm8PCRel) && (inst.mMCInst.getNumOperands() == 2))
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{
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{
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auto immOp = inst.mMCInst.getOperand(1);
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if (!immOp.isImm())
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continue;
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@ -1181,4 +1180,4 @@ bool X64CPU::ParseInlineAsmInstructionLLVM(const StringImpl&asmInst, String& out
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//outError = StrFormat("%s: \"%s\"", diagMessage.c_str(), diagLineContents.c_str());
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return result;
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}
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}
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