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https://github.com/beefytech/Beef.git
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Initial checkin
This commit is contained in:
Brian Fiete
parent
c74712dad9
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078564ac9e
3242 changed files with 1616395 additions and 0 deletions
379
IDEHelper/X86.h
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379
IDEHelper/X86.h
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#pragma once
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#pragma warning(disable:4141)
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#pragma warning(disable:4146)
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#pragma warning(disable:4624)
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#pragma warning(disable:4996)
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#pragma warning(disable:4267)
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#pragma warning(disable:4244)
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#include "DebugCommon.h"
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#include "BeefySysLib/Common.h"
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#include <sstream>
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstPrinter.h"
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#include "llvm/Support/raw_ostream.h"
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#include "CPU.h"
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#include "Debugger.h"
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namespace llvm
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{
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class MCSubtargetInfo;
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class MCRegisterInfo;
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class MCDisassembler;
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class MCInst;
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class MCInstrInfo;
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class MCAsmInfo;
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class MCContext;
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class MCObjectFileInfo;
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}
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NS_BF_BEGIN
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class X86CPU;
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enum X86CPURegister
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{
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// integer general registers (DO NOT REORDER THESE; must exactly match DbgModule x86 register mappings)
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X86Reg_EAX = 0,
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X86Reg_ECX,
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X86Reg_EDX,
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X86Reg_EBX,
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X86Reg_ESP,
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X86Reg_EBP,
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X86Reg_ESI,
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X86Reg_EDI,
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X86Reg_EIP,
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X86Reg_EFL,
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// fpu registers (80-bit st(#) reg stack)
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X86Reg_FPST0,
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X86Reg_FPST1,
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X86Reg_FPST2,
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X86Reg_FPST3,
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X86Reg_FPST4,
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X86Reg_FPST5,
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X86Reg_FPST6,
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X86Reg_FPST7,
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// mmx registers (alias to the low 64 bits of the matching st(#) register)
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X86Reg_MM0,
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X86Reg_MM1,
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X86Reg_MM2,
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X86Reg_MM3,
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X86Reg_MM4,
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X86Reg_MM5,
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X86Reg_MM6,
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X86Reg_MM7,
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// xmm registers
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X86Reg_XMM00,
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X86Reg_XMM01,
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X86Reg_XMM02,
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X86Reg_XMM03,
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X86Reg_XMM10,
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X86Reg_XMM11,
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X86Reg_XMM12,
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X86Reg_XMM13,
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X86Reg_XMM20,
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X86Reg_XMM21,
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X86Reg_XMM22,
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X86Reg_XMM23,
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X86Reg_XMM30,
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X86Reg_XMM31,
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X86Reg_XMM32,
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X86Reg_XMM33,
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X86Reg_XMM40,
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X86Reg_XMM41,
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X86Reg_XMM42,
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X86Reg_XMM43,
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X86Reg_XMM50,
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X86Reg_XMM51,
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X86Reg_XMM52,
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X86Reg_XMM53,
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X86Reg_XMM60,
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X86Reg_XMM61,
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X86Reg_XMM62,
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X86Reg_XMM63,
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X86Reg_XMM70,
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X86Reg_XMM71,
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X86Reg_XMM72,
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X86Reg_XMM73,
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// xmm 128-bit macro-registers (no stored data with these, they're symbolic for use as higher-level constructs, aliases to the individual xmm regs above)
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X86Reg_M128_XMM0,
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X86Reg_M128_XMM1,
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X86Reg_M128_XMM2,
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X86Reg_M128_XMM3,
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X86Reg_M128_XMM4,
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X86Reg_M128_XMM5,
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X86Reg_M128_XMM6,
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X86Reg_M128_XMM7,
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// flags boolean pseudo-registers (aliases to individual flags in EFL)
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X86Reg_FLAG_CF_CARRY,
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X86Reg_FLAG_PF_PARITY,
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X86Reg_FLAG_AF_ADJUST,
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X86Reg_FLAG_ZF_ZERO,
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X86Reg_FLAG_SF_SIGN,
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X86Reg_FLAG_IF_INTERRUPT,
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X86Reg_FLAG_DF_DIRECTION,
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X86Reg_FLAG_OF_OVERFLOW,
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// category macro-registers
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X86Reg_CAT_ALLREGS,
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X86Reg_CAT_IREGS,
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X86Reg_CAT_FPREGS,
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X86Reg_CAT_MMREGS,
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X86Reg_CAT_XMMREGS,
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X86Reg_CAT_FLAGS,
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X86Reg_COUNT,
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X86Reg_INTREG_FIRST = X86Reg_EAX,
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X86Reg_INTREG_LAST = X86Reg_EFL,
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X86Reg_INTREG_COUNT = (X86Reg_INTREG_LAST - X86Reg_INTREG_FIRST) + 1,
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X86Reg_FPSTREG_FIRST = X86Reg_FPST0,
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X86Reg_FPSTREG_LAST = X86Reg_FPST7,
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X86Reg_FPSTREG_COUNT = (X86Reg_FPSTREG_LAST - X86Reg_FPSTREG_FIRST) + 1,
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X86Reg_MMREG_FIRST = X86Reg_MM0,
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X86Reg_MMREG_LAST = X86Reg_MM7,
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X86Reg_MMREG_COUNT = (X86Reg_MMREG_LAST - X86Reg_MMREG_FIRST) + 1,
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X86Reg_XMMREG_FIRST = X86Reg_XMM00,
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X86Reg_XMMREG_LAST = X86Reg_XMM73,
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X86Reg_XMMREG_SINGLE_COUNT = (X86Reg_XMMREG_LAST - X86Reg_XMMREG_FIRST) + 1,
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X86Reg_M128_XMMREG_FIRST = X86Reg_M128_XMM0,
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X86Reg_M128_XMMREG_LAST = X86Reg_M128_XMM7,
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X86Reg_M128_XMMREG_COUNT = (X86Reg_M128_XMMREG_LAST - X86Reg_M128_XMMREG_FIRST) + 1,
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X86Reg_FLAG_FIRST = X86Reg_FLAG_CF_CARRY,
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X86Reg_FLAG_LAST = X86Reg_FLAG_OF_OVERFLOW,
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X86Reg_FLAG_COUNT = (X86Reg_FLAG_LAST - X86Reg_FLAG_FIRST) + 1,
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X86Reg_CAT_FIRST = X86Reg_CAT_ALLREGS,
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X86Reg_CAT_LAST = X86Reg_CAT_FLAGS,
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X86Reg_CAT_COUNT = (X86Reg_CAT_LAST - X86Reg_CAT_FIRST) + 1,
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};
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#pragma pack(push, 1)
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class X86CPURegisters
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{
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public:
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static const int kNumIntRegs = 10;
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static const int kNumFpMmRegs = 8;
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static const int kNumXmmRegs = 8;
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struct IntRegs
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{
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int32 eax;
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int32 ecx;
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int32 edx;
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int32 ebx;
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uint32 esp;
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uint32 ebp;
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int32 esi;
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int32 edi;
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uint32 eip;
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int32 efl;
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};
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struct Fp80Reg
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{
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uint8 fp80[10]; // 80-bit FP value, must be down-converted to use as a double
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};
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union FpMmReg
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{
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Fp80Reg fp;
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int64 mm;
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};
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struct XmmReg
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{
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float f[4];
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};
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struct XmmDReg
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{
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double d[2];
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};
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struct XmmIReg
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{
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int32 i[4];
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};
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union
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{
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IntRegs mIntRegs;
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int32 mIntRegsArray[kNumIntRegs];
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};
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FpMmReg mFpMmRegsArray[kNumFpMmRegs];
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union
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{
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XmmReg mXmmRegsArray[kNumXmmRegs];
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XmmDReg mXmmDRegsArray[kNumXmmRegs];
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XmmIReg mXmmIRegsARray[kNumXmmRegs];
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};
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X86CPURegisters()
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{
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memset(&mIntRegs, 0, sizeof(mIntRegs));
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memset(mFpMmRegsArray, 0, sizeof(mFpMmRegsArray));
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memset(mXmmRegsArray, 0, sizeof(mXmmRegsArray));
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}
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inline uint32 GetPC() { return mIntRegs.eip; }
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inline uint32* GetPCRegisterRef() { return &mIntRegs.eip; }
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inline uint32 GetSP() { return mIntRegs.esp; }
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inline uint32* GetSPRegisterRef() { return &mIntRegs.esp; }
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inline uint32 GetBP() { return mIntRegs.ebp; }
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inline uint32* GetBPRegisterRef() { return &mIntRegs.ebp; }
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inline XmmReg* GetXMMRegRef(int regNum)
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{
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return &mXmmRegsArray[regNum];
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}
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inline int32* GetExceptionRegisterRef(int regNum)
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{
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return NULL;
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}
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static int GetFlagBitForRegister(int flagRegister)
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{
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int flagBit = -1;
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switch (flagRegister)
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{
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case X86Reg_FLAG_CF_CARRY: flagBit = 0; break;
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case X86Reg_FLAG_PF_PARITY: flagBit = 2; break;
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case X86Reg_FLAG_AF_ADJUST: flagBit = 4; break;
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case X86Reg_FLAG_ZF_ZERO: flagBit = 6; break;
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case X86Reg_FLAG_SF_SIGN: flagBit = 7; break;
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case X86Reg_FLAG_IF_INTERRUPT: flagBit = 9; break;
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case X86Reg_FLAG_DF_DIRECTION: flagBit = 10; break;
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case X86Reg_FLAG_OF_OVERFLOW: flagBit = 11; break;
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default: break;
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}
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return flagBit;
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}
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static int GetCompositeRegister(int regNum)
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{
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if ((regNum >= X86Reg_XMMREG_FIRST) && (regNum <= X86Reg_XMMREG_LAST))
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return X86Reg_M128_XMMREG_FIRST + ((regNum - X86Reg_XMM00) / 4);
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return regNum;
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}
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static const char* sCPURegisterNames[];
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static const char* GetRegisterName(int regNum)
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{
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return sCPURegisterNames[regNum];
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}
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};
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#pragma pack(pop)
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class X86Instr
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{
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public:
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X86CPU* mX86;
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llvm::MCInst mMCInst;
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uint32 mAddress;
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int mSize;
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llvm::SmallVector<char, 64> mAnnotationStr;
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llvm::raw_svector_ostream mAnnotationStream;
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static uint8 sRegForm[];
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X86Instr() :
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mAnnotationStream(mAnnotationStr)
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{
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mX86 = NULL;
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mAddress = 0;
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mSize = 0;
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}
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int GetLength();
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bool IsBranch();
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bool IsCall();
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bool IsRep(bool& isPrefixOnly);
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bool IsReturn();
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bool IsLoadAddress();
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bool GetIndexRegisterAndOffset(int* outRegister, int* outOffset); // IE: [ebp + 0x4]
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bool GetImmediate(uint32* outImm);
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int GetJmpState(int flags);
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void MarkRegsUsed(Array<RegForm>& regsUsed, bool overrideForm);
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uint32 GetTarget(X86CPURegisters* registers = NULL);
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};
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class X86CPU
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{
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public:
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typedef std::multimap<String, int> StringToOpcodeMap;
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llvm::MCContext* mMCContext;
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llvm::MCObjectFileInfo* mMCObjectFileInfo;
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llvm::MCSubtargetInfo* mSubtargetInfo;
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llvm::MCRegisterInfo* mRegisterInfo;
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llvm::MCAsmInfo* mAsmInfo;
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llvm::MCInstPrinter* mInstPrinter;
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llvm::MCDisassembler* mDisAsm;
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llvm::MCInstrInfo* mInstrInfo;
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String mWarningString;
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std::stringstream mWarningStream;
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String mCommentString;
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std::stringstream mCommentStream;
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StringToOpcodeMap mStringToOpcodeMap;
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public:
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X86CPU();
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~X86CPU();
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bool Decode(uint32 address, DbgModuleMemoryCache* memoryCache, X86Instr* inst);
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bool Decode(uint32 baseAddress, const uint8* dataBase, int dataLength, const uint8* dataPtr, X86Instr* inst);
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uint32 DecodeThunk(uint32 address, DbgModuleMemoryCache* memoryCache) { return 0; }
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bool IsReturnInstruction(X86Instr* inst);
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String InstructionToString(X86Instr* inst, uint32 addr);
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void GetNextPC(uint32 baseAddress, const uint8* dataBase, int dataLength, const uint8* dataPtr, uint32* regs, uint32 nextPCs[2]);
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bool IsObjectAccessBreak(uint32 address, DbgModuleMemoryCache* memoryCache, int32* regs, int32* outObjectPtr);
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int GetOpcodesForMnemonic(const StringImpl& mnemonic, Array<int>& outOpcodes);
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void GetClobbersForMnemonic(const StringImpl& mnemonic, int argCount, Array<int>& outImplicitClobberRegNums, int& outClobberArgCount, bool& outMayClobberMem);
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bool ParseInlineAsmInstructionLLVM(const StringImpl&asmInst, String& outError);
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};
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#ifdef BF_DBG_32
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#define CPURegisters X86CPURegisters
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#define CPU X86CPU
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typedef X86Instr CPUInst;
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#define DwarfReg_SP X86Reg_ESP
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#define CPUReg_CAT_ALLREGS X86Reg_CAT_ALLREGS
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#define CPUReg_CAT_IREGS X86Reg_CAT_IREGS
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#define CPUReg_CAT_FPREGS X86Reg_CAT_FPREGS
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#define CPUReg_CAT_MMREGS X86Reg_CAT_MMREGS
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#define CPUReg_CAT_XMMREGS X86Reg_CAT_XMMREGS
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#define CPUReg_CAT_FLAGS X86Reg_CAT_FLAGS
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#define CPUReg_FLAG_CF_CARRY X86Reg_FLAG_CF_CARRY
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#define CPUReg_FLAG_PF_PARITY X86Reg_FLAG_PF_PARITY
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#define CPUReg_FLAG_AF_ADJUST X86Reg_FLAG_AF_ADJUST
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#define CPUReg_FLAG_ZF_ZERO X86Reg_FLAG_ZF_ZERO
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#define CPUReg_FLAG_SF_SIGN X86Reg_FLAG_SF_SIGN
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#define CPUReg_FLAG_IF_INTERRUPT X86Reg_FLAG_IF_INTERRUPT
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#define CPUReg_FLAG_DF_DIRECTION X86Reg_FLAG_DF_DIRECTION
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#define CPUReg_FLAG_OF_OVERFLOW X86Reg_FLAG_OF_OVERFLOW
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#define CPUReg_XMMREG_FIRST X86Reg_XMMREG_FIRST
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#define CPUReg_XMMREG_LAST X86Reg_XMMREG_LAST
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#define CPUReg_M128_XMMREG_FIRST X86Reg_M128_XMMREG_FIRST
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#define CPUReg_M128_XMMREG_LAST X86Reg_M128_XMMREG_LAST
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#define CPUReg_MMREG_FIRST X86Reg_MMREG_FIRST
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#define CPUReg_FPSTREG_FIRST X86Reg_FPSTREG_FIRST
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#endif
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static_assert(X86Reg_FPSTREG_COUNT == X86Reg_MMREG_COUNT, "CPUReg register count mismatch"); // these alias to the same regs
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static_assert(sizeof(X86CPURegisters::IntRegs) == X86CPURegisters::kNumIntRegs*sizeof(int32), "X86CPURegisters size mismatch");
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static_assert(sizeof(X86CPURegisters) == (X86Reg_INTREG_COUNT*sizeof(int32) + X86Reg_MMREG_COUNT*sizeof(X86CPURegisters::FpMmReg) + (X86Reg_XMMREG_SINGLE_COUNT / 4)*sizeof(X86CPURegisters::XmmReg)), "X86CPURegisters size mismatch");
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static_assert(offsetof(X86CPURegisters, mIntRegs) == 0, "X86CPURegisters layout mismatch");
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static_assert(offsetof(X86CPURegisters::IntRegs, eax) == 0, "X86CPURegisters layout mismatch");
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NS_BF_END
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